Download electronic version here. EDUCATION Massachusetts Institute of Technology Cambridge, MA PhD, Electrical Engineering Expected June 2012 GPA: 4.9/5.0 Massachusetts Institute of Technology Cambridge, MA M.S., Electrical Engineering June 2009 N.C. State University Raleigh, NC B.S., Computer Engineering B.S., Electrical Engineering May 2007 RELEVANT COURSEWORK Java (Level I & II), Data Structures, Intro to Computer & Electrical Engineering (Circuits, Power, & Signal Processing course), Calculus III, Statistics, Physics, Chemistry, Intro to Computing Systems, Intro to Computer Organization, Fundamentals of Electric Circuits, Analytical Foundations of Computer & Electrical Engineering, Signals & Systems, Digital Logic Design, Technology & Characterization at the Nanoscale, Electromagnetic Fields, Microelectronic Circuit Design, Intro to Embedded Systems, Intro to Solid State Devices, Complex Digital Systems, Digital Signal Processing, Linear Systems, Intro to Computer Communications, Networking, Intro to IC Technology & Fabrication, Controls, Senior Design: Biological Signal Processing, Electromagnetics, Front-End Fabrication, MEMS, Optimization Methods WORK EXPERIENCE Research Assistant: MIT EECS (Advisor, Duane Boning) September 2007-present Massachusetts Institute of Technology Cambridge, MA - Currently focusing on two types of advanced planarization processes: wafer-level modeling of electrochemical mechanical planarization (e-CMP) and die-level modeling of chemical mechanical planarization (CMP) for STI structures using novel slurries. Technical Intern: PTM/IPAG June 2009-August 2009, May 2010-present, Intel Corporation Hillsboro, OR - Researched the possibilities of implementing particle agglomeration models for CMP slurries to understand the causes and effects of agglomerates in planarization. Developed general expression to correlate inter-particle interactions and numerical model framework for correlation of electrochemical properties of the slurry to the probability of agglomeration size distribution. Technical Intern (Part-Time): National Semiconductor June 2008-January 2009 National Semiconductor Corp. South Portland, ME - Currently conducting experiments and performing novel physically based chipscale/feature-scale modeling of STI CMP processes with non-conventional (ceria) slurry types. Electronics Instructor: MIT SEED Academy September 2007-present Massachusetts Institute of Technology Cambridge, MA - Created syllabus, lectures, homeworks, and all lab activities for an equivalent 6.002 course for underrepresented high school students in SEED Academy. Course included the fundamentals of analog and digital circuits, time and frequency domain design, resistive networks, digital logic, and signals. Technical Intern: CTM New Products, Flash Memory Group May 2006-August 2006, May 2007-August Intel Corporation Santa Clara, CA - Researched the possibilities of implementing ULPY die level scoring on flash as an alternative and/or addition to present low yield limits and/or wafer level SBL’s. - Designed and created an automated VA & Perl script [with script host functionality] to pull sort/class data to generate ULPY scores on the die level Conducted data analysis on many permutations of ULPY using my script to show ROI of die level ULPY scoring versus current wafer level methodology. Extern: Retail Sales Champ August 2006-May 2007 Intel Corporation Raleigh,NC - Established relationships with retail managers and sales associates as the sole Intel Champ in eastern North Carolina. - Led trainings and conducted in-store visits in to endorse and inform retail stores about Intel Processor based desktop and notebook platform sales and marketing messages. - Covered 10 retail stores including Best Buy, Circuit City, and CompUSA, consistently having the highest attendance, number of trainings, and Retail Edge numbers in my region. Research Intern: National Nanotechnology Infrastructure Network June 2005-August 2005 Cornell Nanoscale Facility Ithaca, NY - Conducted research under the direction of Professor Sandip Tiwari, director of NNIN & CNF. - Delved into the nanoscale adaptive limits of liquid lenses through the fabrication of silicon/quartz wafers with apertures at the nanoscale. - Trained and experienced on photolithographic processes and tools, chemical/mechanical thin film deposition and etching, making of photomasks, CAD design, & metrology at the micro and nanoscale. Technical Intern: WebSphere Level II, EDGIHS June 2004-January 2005 IBM Research Triangle Park - Created 100+ post install images of WebSphere Application server product. - Designed and created an automated Perl Script which allowed support analysts to recreate customer environments of WebSphere. Setup lab machines with openSSH (password less authentication), openSSL, lsof, GNU compilers, and Perl 5.8. TEACHING EXPERIENCE 6.01: Introduction to EECS I, Teaching Assistant Spring 2010 Massachusetts Institute of Technology - An integrated introduction to electrical engineering and computer science, taught using substantial laboratory experiments with mobile robots. Key issues in the design of engineered artifacts operating in the natural world: measuring and modeling system behaviors; assessing errors in sensors and effectors; specifying tasks; designing solutions based on analytical and computational models; planning, executing, and evaluating experimental tests of performance; refining models and designs. Issues addressed in the context of computer programs, control systems, probabilistic inference problems, circuits and transducers, which all play important roles in achieving robust operation of a large variety of engineered systems. 6 Engineering Design Points. Electronics Instructor Fall 2007/08/09 MIT Saturday Engineering Enrichment Discovery[SEED] Academy - A one semester course in which high school seniors are presented a survey of the high-level flavors of electrical engineering; delving into analog and digital circuits, continuous and discrete time signal theory, digital logic and advance calculus paired with lab projects on breadboards, small robots, and protoboards culminating in final projects that range from low power amplifiers, LED flasher circuits, theremins to electronic dice games. I developed the lectures, labs, and all accompanying materials for this course. E101: Introduction to Engineering & Problem Solving, Teaching Assistant Fall 2005 North Carolina State University - This course is designed to introduce students to the field of Engineering. An objective will be to integrate teamwork, problem solving, and verbal communication skills into a design project within the course in such a way that these skills become the foundation of a successful engineering career. Early understanding of these skills will assist students throughout their undergraduate experience and beyond. Culminates in a Freshman Engineering Design Day, allusory to the Senior Design Day. REVIEW EXPERIENCE IEEE Transactions on Semiconductor Manufacturing, 2010 HONORS & AWARDS MIT Graduate Woman of Excellence Award Recipient [2010] National Science Foundation Fellowship Recipient [2008] MIT Presidential Fellowship Recipient [2007] Intel GEM PhD Fellowship Recipient [2006] Phi Kappa Phi Honors Society Tau Beta Pi, Engineering Honors Society Eta Kappa Nu, ECE Honors Society Roy H. Park Scholar Delta Sigma Theta Sorority, Inc.Resume_CV_files/JoyMJohnson_Resume.docshapeimage_2_link_0